After the HP broadcast on the future of the 3000, there was some much
confusion and difference of opinion/perception of what was or was not
said, especially since there was only one brief reference to IA-64.
I e-mailed Harry Sterling and Kriss Rant for clarification, and later
received a follow-up from Dave Snow. After receiving permission from
hom to share his response, I am now attaching it below with a few
clarifications/emphasis included in square brackets [] from me.
Jeff Kell <[log in to unmask]>
------------------------reply from Dave Snow---------------------------
Hi Jeff, I'm Dave Snow, Platform Planning Manager for CSY, and Kriss
and Harry asked me to address your clarification request.
Your message basically asked on what architectures and on what
processor chips within these architectures will MPE/iX be supported on
in the future.
Before I get too specific, let me give some definitions.
Within this discussion, there are three architectures of interest:
PA-RISC 1.x (including 1.0, 1.1 and 1.2)--These are all
variations on the original HP PA-RISC architecture designed in
the early 1980's and which began shipping in the mid-1980s. It
was designed as a 64-bit segmented architecture but with the idea
that its 32-bit flat addressing space would be extended to >32
bit someday.
PA-RISC 2.0--This is the latest PA-RISC architecture designed
around 1991. The first PA-RISC 2.0 processor chip is the PA-8000
which began shipping as evaluation chips in 1995 and in HP
systems in 1996. Chips using this architecture support both a
1.x mode and a 2.0 mode. The 2.0 mode takes the flat addressing
portion of the segmented addressing space and expands it to
64-bits.
IA-64 (formerly known as HP SPPA)--The next generation HP
architecture, SPPA, was designed by HP in the early 1990s. After
some discussions with Intel, the architecture was jointly
redesigned by Intel and HP and renamed IA-64. Chips should be
available from Intel by the end of the decade. This is also a
64-bit architecture and will also execute previous HP PA-RISC
code and previous Intel x86 code. At this time, Intel is the
only one who can give out details of the architecture.
Within these architectures there are various chip implementations that
are identified by various names (PA-7200, PA-8200, Merced). Here are
some of them in a matrix showing released servers.
MPE/iX Servers HP-UX Servers NT Servers
PA-RISC 1.x:
PA-7100 987; G50; H50; I50; None
987/150; G60; H60; I60;
987/200; G70; H70; I70;
991; 995; T500;
PA-7100LC 9x8; E-Class None
PA-7150 996; T520 None
PA-7300LC None D-Class None
PA-7200 939KS; 959KS K100; K200; K400; None
969KS/x00; K210; K410;
969KS/x20; K220; K420;
PA-RISC 2.0:
PA-8000 979KS: K250; K450; K460 K460; None
Planned 99x; Planned T-Class;
PA-8200 Planned: Planned; None
PA-8500 Planned; Planned; None
IA-64:
Merced Possible; Planned; Planned
Chip #2 Possible Future; Future; Future
[In my original question, I referred to Dave's "Chip #2" as "Superchip"
being the Merced follow-up, for lack of a better name - JK]
HP does not have a program underway called "Superchip". Any
references you may have heard to an architecture which is a "merge of
the PA-RISC/Intel" architectures is a reference to the HP/Intel
architecture known as IA-64 of which Merced is the first processor
chip. The term "Tahoe" is an internal HP term and references some
projects that are related to IA-64.
[I also asked if IA-64 meant the end of PA-RISC - JK]
Regarding obsolescence or discontinuance precedences for processor
chips. We discontinue production of a processor chip when the demand
does not warrant continued production. At that time we forecast the
remaining lifetime requirements for the chip (including both future
sales, upgrades and the multi-year requirements of the support
channel), make final builds of the chips and then distribute these
chips to the various using organizations for warehousing. Because of
this, we do not see any problem in having enough processor chips in
the pipeline from either the fabrication lines or the warehouses to
meet our needs. Keep in mind that once we discontinue a server
product line, HP has to be able to support it for a minimum of 5
years. Availability of processor chips will not be an issue.
CSY did not say we would not port MPE/iX to the IA-64 architecture.
[^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^]
Instead we said that we know what it would take to do such a port and
that "at this time", such a port is "not a high priority." We believe
that for the foreseeable future, that the PA-RISC architecture will
meet our customers' business needs. We expect additional servers
based on the PA-8000 to be introduced in 1997, servers based on the
PA-8200 to be introduced in 1998, and severs based on the PA-8500 to
be introduced in 1999. We also have the possibility of PA-RISC chips
beyond the PA-8500 to be introduced beyond the year 2000. We are also
working on other platform extensions such as more I/O slots and higher
performance I/O buses which we believe could become limiters to our
customers' HP 3000 server growth during the rest of this decade.
Our efforts during the rest of this decade are focused on meeting our
customers' current business requirements while investing in such a way
that we can also meet their future business requirements during the
next decade. Investing in the Year 2000 arena and at the same time
investing in PA-RISC processors that will be introduced in 1999 or 2000
are both examples of efforts to meet the business needs of our
customers in the next decade.
Hope this helps. Give me a call if this raises additional questions
keeping in mind that with futures, I'm limited in what I can say.
Dave Snow
HP 3000 Platform Planning Manager
|
