Gavin writes:
>My guess is that what he meant was that the new *systems* that are built
>with the HP/Intel chip will provide binary compatibility with the previous
>versions of those systems. I don't expect to see a chip which can execute
>'new' instructions and PA-RISC inscructions and Intel P6 instructions
>all on its own. The architectures are just too different. An HPUX system
>built with the new chip will probably provide a PA-RISC 'Compatibilty
>Mode' just like the PA-RISC based MPE/iX systems provide an MPE/V
>Compatibility Mode.
 
It is very likely that especially for PA-RISC, there will be considerable
emulation help in silicon. PA-RISC can achieve efficient emulation of
16-bit HP3000 instructions because the small instruction size allows
arbitrarily complete instruction decoding in a single cycle and because the
number of machine cycles required for emulation of an instruction is
roughly the same as the number required for execution on the original
machine. A system hoping to emulate a PA-RISC architecture has neither
advantage.
 
On the other hand, efficient emulation of the x86 architecture will be
considerably easier. In effect, this is what the P6 and the Cyrix and AMD
Pentium-type processors are doing already. (One wonders what could happen
if Intel directly exposed the P6 micro-architecture, allowing micro-ops to
be dispatched either from the translator or the instruction cache. In
essence, the P6 is a powerful RISC processor forever condemned to execute a
large collection of silly little programs.)
 
-- Bruce
 
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