Glenn writes: > 2. slide 14, "IA-64 Floating Point Architecture" > > highlights the "Freddie Mac" (my term) instruction: > FMAC = Floating-point Multiply/ACcumulate = a * b + c Of which there are allegedly four in Merced, giving it 6 gigaflop FP performance. > The odd thing here (to me) is that floating point numbers > are 82 bits. The hardware supports 80 bit extended precision floating point. This is perhaps the most commonly used data size for numerical scientific calculations these days I guess. 64 bits isn't enough, but 128 bits is too expensive :-) I haven't seen the 82 number yet, though in memory they are definitely only 80. > 3. slide 16, "IA-64 Compatibility with PA-RISC Through Dynamic Translation" > > (IA-32 compatibility is through hardware, mentioned on slide 6.) And the hooks are there to eventually remove it. > explicitly states "Bundled with HP-UX"; no mention of MPE. > <sigh> The fight goes on.... Well, I don't think CSY has decided how they are going to do things for sure yet, though the dynamic translation seems like the most likely scenario for most of MPE at least initially. > Under the "Performance" bullet, it notes > "1:1 mapping of PA-RISC to IA-64" Haven't read through the instruction set yet, and the released documentation does *not* cover the supervisor-mode features of the architecture. For example there is *no* discussion of Virtual Memory! I've always suspected though that it is going to look a heck of a lot like PA-RISC 2.0, since that would almost be required to do the dynamic translation stuff. Maybe there's another document I haven't found yet though. > "Open source software enabling" is shown to coincide with > the "IA-64 Architecture Public Release", which was today. What's been released today (at least what I've seen so far) is seriously deficient if you're trying to write an operating system, though it may be all you need if you're only going to be writing application programs. G.