John,

John D. Alleyn-Day <[log in to unmask]> wrote I presume that this means
that the
> 64-bit virtual addressing that is being discussed for large files would
be
> incorporated using only 32-bit addressing on the chip, so that it would
be
> available to all MPE/iX systems (or maybe MPE would use 64 bits on the
2.0
> chip and 32 bits on the 1.x chip?).  Am I right - or will use of large
> virtual address spaces necessitate a move to the 8000 series chip?

In a hallway discussion at IPROF Birkett proposed to one HP rep that the
type of customer that needs large (> 4G) files is already a PA-8xxx /
RISC-2 customer, is already planning on becoming one, or wouldn't have a
problem becoming one to get that feature.

    IF  HP finds a solution that is much better or easier to implement only
on the RISC-2 architecture then I suggest that HP implement it only for the
new RISC-2 CPUs.
     It seems to me that my small and mid-sized clients don't have a
pressing need for large files on their '3000s and therefor they are best
served by the solution that uses the least development funds and leaves
more funds available for other features.  Does anyone have a problem with
this?

HP is really serious about compatibility (which is usually very good) so
this idea is radical to them.

- Cortlandt