At 10:26 AM 5/7/97 -0700, Gavin Scott wrote:

>Now, one of the cool things about the PA-RISC 2.0 architecture is
>that even though all the general registers in the CPU have expanded
>for 32bits to 64bits, all existing PA-RISC 1.x code that expects
>there only to be 32bits per register runs correctly.

.........................................

>Because of the inherent compatibility between the 32bit PA-RISC 1.x
>CPUs and the 64bit PA-RISC 2.0 CPUs, it probably wasn't that hard
>for HP to get MPE running on the new systems.

.............................................

Thanks for the explanation, Gavin.  I thought I was missing out on
something here.  One more question.  I presume that this means that the
64-bit virtual addressing that is being discussed for large files would be
incorporated using only 32-bit addressing on the chip, so that it would be
available to all MPE/iX systems (or maybe MPE would use 64 bits on the 2.0
chip and 32 bits on the 1.x chip?).  Am I right - or will use of large
virtual address spaces necessitate a move to the 8000 series chip?

John D. Alleyn-Day
Alleyn-Day International
408-286-6421   408-286-6474 (Fax)
[log in to unmask]       http://www.Alleyn-Day.com