HP3000-L Archives

November 1997, Week 3

HP3000-L@RAVEN.UTC.EDU

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Gavin Scott <[log in to unmask]>
Reply To:
Gavin Scott <[log in to unmask]>
Date:
Wed, 19 Nov 1997 14:39:21 -0800
Content-Type:
text/plain
Parts/Attachments:
text/plain (66 lines)
Jeff after Glenn:
> |Is IA-64 a superset of PA-8000?
>
> The folks at Allegro (or whatever name they're using today :) are not
> being overly helpful this time, are they?  ;)

We were going to call ourselves the Frobozz Magic Software Company today
but there already seems to be an actual company by that name so I guess
we're stuck with Allegro.

> IA-64 is the first chip which will be (is being?) produced as a result HP
> and Intel's joint effort to develop a successor to both the HP-PA and x86
> processor lines.  I believe it has been known as the Merced processor, but
> these days IA-64 is the name generally used for it.

I believe Merced is/was the code name for the first implementation of the
new arcitecture.  IA64 is the official Intel name for the architecture
itself I believe.  I don't think they have announced a real pruduct name
(like "Pentium") for the Merced chip[(s)?] yet.

> One of the things I think I know about it (meaning that I'm not sure of it)
> is that it will have a completely new instruction set.

Yes, it has an entirely new instruction set.  HP and Intel announced some
details of how the system will work last month, and the December BYTE
presents this information in some detail.  Many significant details (most
notably procedure calling conventions) have not yet been disclosed.  The
newsgroup comp.arch is a good place to watch for new details (and lots of
wild speculation).

> It's expected to
> be able to emulate HP-PA and x86 instructions at speeds comparable to native
> execution on the native processors in the same way that HP-PA boxes could
> execute classic (CM) 3000 code at speeds even faster than the old classic
> boxes could achieve.

Exactly how they intend to do this is not clear yet.  For example, we don't
know whether the same mechanism will be used for both IA-32 (Intel x86) and
PA-RISC "compatability", or how much hardware support is being provided.  A
couple of patent applications were circulating on the net a while back that
gave some clues however.  Even emulating an old architecture completely in
software isn't that hard when your new chip runs at 700Mhz or more.

The PA-8000 is the first PA-RISC chip that implements the PA-RISC 2.0
specification which extends PA-RISC to 64 bits.  PA-8x00 chips are
currently being used in the higher end HP3000 and HP9000 systems.  The
PA-8x00 chips are fully upwards compatible with the earlier ~32 bit
PA-RISC chips.  HP-UX 11.0 is the first operating system from HP that
makes significant use of the 64 bit features of these new CPUs.

Once again, the IA-64 chips are completely different from any PA-RISC
chip, including the PA-8000.  No IA-64 chip is yet available.  PA-8000
chips have been shipping in HP9000 and HP3000 systems for some time.

Some off the top of my head numbers:

                            PA-RISC 1.x  PA-RISC 2.0  IA-64
                            -----------  -----------  --------------------
Max Physical memory:        3.75Gb       insane amt.  insane amt. (we assume)
# of General Registers:     32           32           128
# of Floating Point Regs:   16 or 32     32           128
Size of General Registers:  32 bits      64 bits      64 bits (I believe)
Instruction size (bits):    32 bits      32 bits      3 packed into 128 bits.
                                                      if I understand right.
G.

ATOM RSS1 RSS2