HP3000-L Archives

May 1997, Week 3

HP3000-L@RAVEN.UTC.EDU

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Subject:
From:
Bill Lancaster <[log in to unmask]>
Reply To:
Bill Lancaster <[log in to unmask]>
Date:
Fri, 16 May 1997 09:11:24 -0400
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The MHz rating of a processor is a bit of a red herring in terms
of performance.  The clock speed is only one metric and doesn't truly
reflect the actual *throughput* of the system.  HP is reporting better
throughput with the PA8000 chipset at 180 MHz than 400+ MHz Alpha
boxes.  Gavin is probably much more equipped to answer this but
I expect that the combination of multi-stage pipelining, pre-fetch
miss cache, large instruction caches and large data primary off-chip
caches (on a per-processor basis) combine to actually getting
lots of work done.

To quote an HP document:

"These caches operate in a write-back mode.  Write-back means that
the cache writes modified data to system memory only when the
processor needs the cache location for other data or when the
operating system flushes the cache location due to a direct
memory access operation.  This efficient cache operation
provides maximum server throughput."

and

"Instruction pipelining is a technique that overlaps instruction
processing so that one instruction can begin to execute before the
previous one has finished.  Excluding penalties for cache misses
and for branch instructions, the net effect is that one instruction
can complete the pipeline with essentially every instruction clock
cycle. The PA-8000 utilizes a five-stage pipeline.

"In addition, the PA-8000 processor supports dynamic scheduling of
instructions with a 56-instruction deep queue.  This controlled,
out-of-order execution of instructions is important to optimizing
the PA-8000 processor's superscalar operation."

"Superscalar operation in the PA-8000 processor chip allows up to
four instructions to be concurrently pipelined every 5.6 nsec
instruction clock cycle."

In addition to these features, the hardware offers other
significant hardware performance features in the memory and
I/O subsystem.  On the software side, MPE/iX does an outstanding
job of eliminating a relatively huge amount of physical disk
I/O due to software data prefetching.  Most of the systems I
have seen, and still see, have a read-type I/O elimination of
95 percent or greater.

The unfortunate thing about attempting to compare HP 3000
performance to other, non-HP systems is that the only realistic
way to do it is via some of the business-oriented benchmarks
in the TPC suite.  Unfortunately, HP no longer performs these
benchmarks in the 3000 line due to decisions to spend the money
in other areas.

Hope this helps.

Bill Lancaster

At 06:20 PM 5/15/97 -0600, F. Alfredo Rego wrote:
>Bill Lancaster <[log in to unmask]> wrote:
>
>>The 997 (up to 5-way) is orderable now with shipping beginning in
>>September.  HP expects to be able to go greater than 5-way sometime
>>in 1998.  The 997 processor runs at 180 mhz which, apparently, causes
>>some problems above the 5-way level.
>
>What?  180 MHz?  My trusty Mac PowerBook 3400c laptop runs at 240 MHz.
>Surely HP can do much better than 180MHz for a top-of-the-line Enterprise
>Server HP3000...
>
>
>What's up (or down)?
>
>
> _______________
>|               |
>|               |
>|            r  |  Alfredo                     [log in to unmask]
>|          e    |                           http://www.adager.com
>|        g      |  F. Alfredo Rego               Tel 208 726-9100
>|      a        |  Manager, R & D Labs           Fax 208 726-2822
>|    d          |  Adager Corporation
>|  A            |  Sun Valley, Idaho 83353-3000            U.S.A.
>|               |
>|_______________|
>
>
>                                                                .
>
>
>
>
>

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