After responding to Glenn's post noting the unveiling of the new HAL-15
"desktop" computer, someone, apparently working for a news clipping service,
gathered up my post and a few others and mailed them back to Star Bridge
Systems. Whoever it was was courteous enough to mail a copy of the entire
assemblage to me too (and I presume everyone else on the list).

I thought I would share one of the comments that he/she collected, in this
case one that appeared on the comp.arch.fpga newsgroup. If nothing else the
posting has a link to a picture of the innards of the HAL-15 "hypercomputer":

=======================================

From: Jean-Marie Bussat ([log in to unmask])
Subject: Re: HAL-15
Newsgroups: comp.arch.fpga
Date: 2001-03-30 14:02:24 PST

Hi,

If you follow the link, you can have a good idea of what the thing
is. I think that the word "hypercomputer" is somewhat inapropriate.
This development may lead to a kind of hypercomputer but for now,
this is just something that uses the old idea of using FPGAs as
reconfigurable coprocessors.

On the picture http://acmb.larc.nasa.gov/olaf/inhal34.jpg you can
clearly see that HAL is in fact a "normal" PC motherboard (you
can just see the edge of the board but I don't think that there is
anything special on it) connected to a PCI expansion board filled
with FPGA. Unless there is something else not described, that's it.

The few snapshots of the "user interface" to HAL show a GUI where
it seems that you can place functional blocks such as mathematical
functions and connect them together.

I think that there should be a kind of "compiler" that should use
a set of pre-written vhdl/verilog libraries where each functional
block is described. Kept hidden from the user, there should be a
Xilinx synthetizer/optimizer that should compile the resulting
vhdl code and download the bitstream to the FPGAs.

I guess they should also have written a set of standard functions
to interface the HAL board to the PC.

By the way, everything here is pure extrapolation from the few
amount of available information. This is also how I saw things
when I started to think about reconfigurable coprocessor made
using FPGA (but in my case I was thinking about neural networks
applications).

Anyway, I think that this stuff should work and giving enough
time to them to finalize the interface, they should be able to
produce something that would completely hide the FPGAs to the
end user. But we are still far from a 100% FPGA based
"hypercomputer"...

Jean-Marie Bussat
 _______________________________________
 |                                       |
 | Jean-Marie Bussat                     |
 | Lawrence Berkeley National Laboratory |
 | 1 Cyclotron Road - MS 50A-6134        |
 | BERKELEY, CA 94720 - USA              |
 | Email: [log in to unmask]               |
 | Phone: (510)-486-5687                 |
 | Fax:   (510)-486-5977                 |
 |_______________________________________|

=======================================

As I mentioned earlier, this technology has simply exploded in the last
decade because of the arrival of FPGAs as a hardware foundation for a very
useful paradigm that may well become in the next twenty years the dominant
architecture for most computers, and almost certainly supercomputers. While a
database engine such as the HP3000 is very likely to always remain a von
Neumann-architected device, reconfigurable/adaptive/evolvable machines are
very likely to become the preeminent construct for almost any other form of
computation, especially in those machines and circumstances that involve
optimization or the simulation of complex problem spaces, such as fluid
dynamics, speech, vision, language and learning.

There is a particularly nice, succinct German web page that explains much of
the general idea in just a few words (and their picture looks very much like
the link above):

       http://www.gmd.de/BIOMIP/HTML/Research/EvoHard.html

Wirt Atmar