Mark writes:
> 4-way superscalar, means, I think, that there are 4 "stages" in the
> execution pipline of the CPU, so up to 4 instructions can be loaded in
> the execution pipeline at one time, each one at a different stage of
> execution.

"Superscalar" means the processor is able to execute as many as N (where N=4
in this case) different instructions per cycle (given that all needed
operands are in registers and sufficient processor resources are available.

So a non-superscalar, 1GHz CPU would typically have a "peak instruction
rate" of one billion instructions per second, and a "4-way superscalar" CPU
running at 1GHz would have a peak instruction rate of four billion
instructions per second.

Of course memory bandwidth and other things will conspire to prevent
reaching these maximums most of the time.

Modern PA-RISC CPUs are what are called "out-of-order" (OOO) implementations
where the chip pulls in instructions in the order that they exist in the
program, but can hold a number of them (56 I believe for the PA-8700) at
once, and will rearrange the actual execution order so as to optimize the
utilization of the instruction functional units available.  This allows the
chip to efficiently execute instruction streams that were not perfectly
optimized for that particular CPU chip, and better utilize the "superscalar"
nature of the implementation..

IA-64 on the other hand uses the idea of Explicit Scheduling, where the
compiler understands exactly what functional units are available in the CPU
and issues instructions that are pre-arranged for optimal execution.

G.

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