In article <[log in to unmask]>, [log in to unmask]
says...
> Further, the Itanium chips had an emulation mode which could run
> native PA-RISC and native x86 instructions without recompiling.
> However, there was a non-trivial performance hit for that.

I looked for that PA-RISC emulation mode once and all I could find was
some 3rd party software that emulated the PA-RISC chip.  I couldn't find
anything on the Intel website or anywhere else that suggested some sort
of on-chip emulation.  I'd be interested if you had more info.

I'm not sure about the x86 - I didn't look for that but it sounds more
likely to be a proper emulation mode.

> > The Xeon 64 bit chip will run both 32 bit code and 64 bit code.
>
> Yes, but will there be a performance penalty for one or the other?

I looked into this too.  Given that you have a 64 bit chip that can run
32 bit code - it will run the 32 bit code quicker.  Given a 64 bit chip
with the same amount of cache and the same clock speed and general
design as the 32 bit chip, the 64 bit chip will run the 32 bit code at
exactly the same speed as the 32 bit chip but will still run the 64 bit
code slower.  But most 64 bit chips come with more cache so when you
compare a 32 bit and 64 bit CPU, the 64 bit one will perform better.

That's not looking at any advantages you can make with the higher
address space or more bits/clock cycle maths calculations.  i.e. no
source code changes.

Interesting to read your comments about HP and thier direction.  I
always worry that they'll suddenly decide to go back to PA-RISC when
we're all trying to get used to itanium but it sounds unlikley after
reading what you have to say.

Peter

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