Gavin points to IA-64 details:

>   http://www.hp.com/go/ia64
>   http://developer.intel.com/design/ia64/downloads/adag.htm

I had a chance to go through the marketing-oriented info (ONE of the items
available at the first link) entitled "IA-64 Architecture Presentation"

    http://209.207.142.135/ia-64/high_level_press.ppt

(a PowerPoint slide show).  Some interesting tidbits from that:


1. slide 5, "High End IA Roadmap"

        shows a 2-D graph of future processors (IA-32 and IA-64),
        with the vertical axis labelled "Performance**".  Of course,
        since they note "** Not to scale," this axis is meaningless.

        The most interesting thing here is the divergence after
        McKinley (which is the sole successor to Merced).  One path
        (Madison) takes the strict performance route, while the other
        (Deerfield) goes for price/performance.

        Note that the price/performance target is not until 2002.


2. slide 14, "IA-64 Floating Point Architecture"

        highlights the "Freddie Mac" (my term) instruction:
        FMAC = Floating-point Multiply/ACcumulate = a * b + c

        The odd thing here (to me) is that floating point numbers
        are 82 bits.


3. slide 16, "IA-64 Compatibility with PA-RISC Through Dynamic Translation"

        (IA-32 compatibility is through hardware, mentioned on slide 6.)

        explicitly states "Bundled with HP-UX"; no mention of MPE.
        <sigh> The fight goes on....

        Under the "Performance" bullet, it notes
        "1:1 mapping of PA-RISC to IA-64"


4. slide 19, "Merced Industry Rollout"

        shows the final "Production Solutions" step occurring around
        mid-2000.

        "Open source software enabling" is shown to coincide with
        the "IA-64 Architecture Public Release", which was today.

FWIW.

--Glenn