For those of us interested in such things:
 
     According to an article in the InterexPRESS for March, HP will release
     its first systems using a new PA-8000 chip, which is apparently a true
     64 bit version of PA-RISC (PARISC version 2.0), in the fourth quarter
     of 1995.
 
     The chip apparently brings 50 instructions onto the CPU from cache in
     a chunk and then works out what order to execute them in to minimize
     interlocks and other resource contention. The chip is four-way
     superscalar, which means it can execute four instructions every clock
     cycle.
 
     It is said to be object code compatible with existing code and uses
     the same bus interface as the new PA-7200 chip (used in the KS server
     3000s just announced), which will potentially allow for an easy
     upgrade path.
 
     A PA-8200 chip with a higher clock rate and more 64bit enhancements is
     supposed to be available 12-18 months later.
 
     No mention of whether they plan to use this chip in HP3000 systems in
     addition to the HP9000 series, though it sounds as though MPE/iX
     should be able to take significant advantages of this new
     architecture, even if it is not changed to take advantage of the 64
     bit features right away.
 
     G.