Hi, BRUCE

PS. IIRC PICO Second is10**-12 Second = 1ns/1000

HP change TTL, CMOS to ECL , but they stuck with Hardware clock 
barrier again, so, They change to CISC microprogram to RISC to
compensate their slow MOS.clock cycle..

Other side, INTEL keep improving their clock cycle with CISC, 
but, now INTEL seems like hit the barrier to change Microprogram 
to RISC...

Deja vu 

Peter C.


SR. ERP/MRP Analyst

>>> Bruce Toback <[log in to unmask]> 10/06 2:12 PM >>>
Gavin wrote:

>The 930 CPU ran at a whopping 8MHz, which was pretty good considering that
>a series 70 was something like 1 or 2Mhz I believe.

The Series 64/68/70 ran at 13.3MHz (75ns microcycle time). It did this by
using emitter-coupled logic (ECL), which is expensive, power-hungry and
difficult to work with. ECL is used today, but typically in circuits that
run at several GHz, primarily in communications equipment -- see, for
example, <http://www.mot-sps.com/logic/1330_firstpg.html>. ECL is also
used to "glue" subsystems together in fast microprocessor-based
computers, since it offers processing delays of less than 500ps.

-- Bruce


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