> 4-way superscalar, means, I think, that there are 4 "stages" in the
> execution pipline of the CPU, so up to 4 instructions can be loaded in
> the execution pipeline at one time, each one at a different stage of
> execution.

Not quite. Almost all the posts I've seen on this treat "4-way" as a
modifier of "superscalar". It isn't. Both are modifiers of "CPU", though
the "4-way" should actually be applied to the "CPU module" used by the
SuperDome--a card with 4 CPUs on it.

The PA-8700 CPU has 10 execution units; two integer ALUs, two
Shift/Merge units, two FP MAC units, two FP Div/SQRT units, and two
Load/Store units (one for even addresses, the other for odd). Under
ideal conditions, it can retire 4 instructions per clock cycle. On its
way from Instruction Cache to the Retire Unit, an instruction will pass
through Instruction Fetch/Decode, Sort, one of two Reorder Buffers, one
of the above-mentioned execution units, and may also use the services of
the Address Reorder Buffer, TLB, and one or more Rename Registers.

My understanding is the PA-8700 is not "superpipelined" in the way that
Intel processors are, where the execution path may involve up to two
dozen micro execution units, each of which performs part of the work of
executing a single instruction. IOW, the "superscalar"
multiple-instructions-per-clock execution of the PA-8700 is not achieved
by sequencing little pieces of multiple instructions through the pipe,
but rather by having multiple instructions issued to the various
execution units each cycle.

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