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News.Com has lots more info than yesterday's press release. Check out

        <http://www.news.com/News/Item/0,4,15255,00.html>

The big surprise (for me) is that the director of the Measurement,
Architecture, and Planning Group at Intel, Fred Pollack, emphasizes
the *follow-up* to Merced. Scheduled to be released in 2001, this
second-generation Merced will "knock your socks off" and double
performance, according to Mr. Pollack.

Somehow, I thought the FIRST generation was supposed to "knock my
socks off."

(Don't look for 32-bit computing to go away anytime soon. Mr. Pollack
has a chart that shows 32-bit chips scheduled to be released in 2003.)

To really take advantage of this chip, it appears that compiler technology
will be all-important. (Remember, the "parallel" part of this architecture
is "EXPLICITLY parallel." Who do you think has to be explicit?)

An analyst at Dataquest, Martin Reynolds, says:

        "The question you have to ask is, 'If this is so great
         why hasn't it been done before?' The reason is that
         the compilers were so scary to do."

I wonder why he uses the past tense, as in "compilers WERE so scary."

Anyway, it's an interesting read, though (for me) it raises more
questions than it answers.

--Glenn Cole
  Software al dente, Inc.
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